In 2022, the semiconductor industry will enter the mass production stage of the 3nm process. In the first half of the year, Samsung announced the mass production of 3nm chips, but the customers and output were very limited. In the second half of the year, TSMC also began to mass produce 3nm chips, but it was limited to some new mobile phones of Apple. Processors, similar to Samsung, TSMC did not achieve mass production in the first year. The output of 3nm process chips depends on the performance and yield performance of Samsung and TSMC’s upgraded versions in 2023.
3nm mass production is so difficult, and the next 2nm and 1nm nodes will be more challenging, especially 1nm, which has reached the limit of the nanoscale process node, and if it evolves forward, it will be Angstrom (A, 1nm=10A). Therefore, who can do a good job in the research and development and mass production of 1nm process technology and launch it first in the industry will have a strong symbolic meaning.
According to the development roadmap planned by IMEC (Belgian Microelectronics Center), it is expected that mass production of 1nm process technology will be realized in 2028, A7 (0.7nm) in 2030, and then A5, A3, and A2 processes respectively.
The ultimate node battle in the nano-process era begins
However, the change in the metal gate pitch index that really determines the process density is not as large as the process number. Even the A7 to A2 process technology is between 16nm-12nm, and the density may not increase much. Moreover, when it reaches near the 1nm node, the quantum tunneling effect generated may invalidate the traditional semiconductor process.
In addition, to achieve 1nm and below process technology, the transistor structure must also be changed. Samsung and TSMC have given up FinFET at the 3nm and 2nm nodes respectively and turned to the GAAFET structure. After 1nm, the industry will generally turn to the CFET transistor structure. Not only transistors, but other related technologies also need to be upgraded, such as wiring, lithography machines, etc., which require a series of technological breakthroughs to be possible.
new transistor architecture
The transistor architecture used by Samsung 3nm is GAAFET, also known as Nanosheet, and the 1nm process puts forward higher requirements for the transistor architecture. IMEC proposed Forksheet. In this architecture, the sheet is controlled by a fork-shaped gate structure. Before gate patterning, it is realized by introducing a dielectric layer between PMOS and NMOS. This dielectric layer physically isolates the The P-gate trench and the N-gate trench make the N-to-P pitch closer than FinFET or Nanosheet. Through simulation, IMEC expects Forksheet to have ideal area and performance scaling, as well as lower parasitic capacitance.
In addition, 3D “complementary FET” (CFET) is also a transistor solution for 1nm process. A striking feature of CFET technology is the strong similarity to the nanosheet topology. The novelty of the CFET lies in the vertical placement of the PFET and NFET nanosheets. The CFET topology utilizes typical CMOS logic applications where a common input signal is applied to the gates of the NFET and PFET.
The ultimate node battle in the nano-process era begins
The CFET architecture requires special attention to the formation of PFETs and NFETs. SiGe epitaxial growth for PFET source/drain is used to introduce compressive strain in the channel to enhance hole mobility, followed by PFET gate oxide and metal gate deposition, followed by NFET source/drain node Epitaxial Si growth, subsequent gate oxide and metal gate deposition must obey the material chemistry constraints imposed by existing PFET devices.
New material technology
In the manufacturing process of advanced process chips, the front process is responsible for manufacturing transistors with corresponding structures, while the intermediate process and subsequent process are to connect these independent transistors to achieve the corresponding chip functions and performance, which requires the use of to various semiconductor materials.
The 1nm process requires the support of new transistor architectures, such as Forksheet and CFET, which put forward higher requirements for local interconnection. Correspondingly, new materials (such as ruthenium (Ru), molybdenum (Mo), etc.) need to be used in subsequent processes. There is also a need to reduce contact resistance in intermediate processes.
The resistance and capacitance of metal lines and vias are still the most critical parameters for back-end process, and one way to solve this problem is to use another metallization structure called “zero via mixed height”. This solution can flexibly replace resistance with capacitance according to the application requirements of the metal wire.
In order to meet the requirements of new transistor structures while further relieving wiring congestion, further innovations in intermediate processes are required, for example, in CFETs, new solutions for contact gates are required. In addition, vias with high aspect ratios interconnect various components. Currently, these components have been extended to three dimensions (3D), however, there is a need to reduce the parasitic resistance of these deep vias, which can be achieved by introducing advanced contacts , for example using ruthenium.
In the past, three-dimensional materials were mostly used in chip manufacturing. In recent years, under the leadership of leading manufacturers represented by TSMC and Intel, two-dimensional (2D) materials have gradually entered the mainstream.
In 2021, TSMC, in cooperation with Taiwan University of China and the Massachusetts Institute of Technology (MIT), discovered that two-dimensional materials combined with the semimetal bismuth (Bi) can achieve extremely low resistance, close to the quantum limit, and can meet the needs of the 1nm process. The thickness of two-dimensional materials can be less than 1nm, which is closer to the limit of the thickness of solid-state semiconductor materials. The characteristics of bismuth, a semi-metal, can eliminate the energy barrier at the interface with two-dimensional semiconductors, and the atomic structure of two-dimensional materials will not be destroyed during deposition. In this way, through a two-dimensional material with only 1 to 3 layers of atomic thickness (less than 1nm), electrons go from the source (source) to the electron channel layer made of molybdenum disulfide, and there is a gate (gate) above to control the voltage. Then flow out from the drain, using bismuth as the contact electrode can greatly reduce the resistance and increase the transmission current, making the two-dimensional material a new type of semiconductor material to replace silicon in the implementation of the 1nm process technology.
Recently, researchers at the Materials and Manufacturing Institute (MMFI) at the University of New South Wales in Sydney used free-standing single-crystal strontium titanate (STO) films to fabricate a series of transparent field-effect transistors with performance comparable to current silicon semiconductor field-effect transistors . This semiconductor material process overcomes the limitation of silicon in miniaturization, while demonstrating the potential for large-scale fabrication of 2D field-effect transistors, overcoming the challenges of nanoscale silicon semiconductor production, and providing reliable capacitance and efficient switching operation.
According to the researchers, the key innovation of this work is to transform the traditional 3D bulk material into a quasi-2D form without reducing its performance, which means that it can be freely assembled with other materials like Lego bricks for various Emerging and undiscovered applications create high-performance transistors.
In addition, in 1nm process chips, the Joule heating effect caused by metal interconnection is an important consideration. In this regard, IMEC has proposed a new solution. The 1nm process requires the introduction of new conductor materials such as binary and ternary intermetallic compounds (Al or Ru compounds) at the most critical layers on the back end, which have lower resistivities than conventional elemental metals (e.g. Cu, Co, Mo or Ru). IMEC has experimentally studied the resistivity of aluminide films, including AlNi, Al3Sc, AlCu and Al2Cu. At a thickness of 20nm and above, the resistivity of all PVD deposited films is comparable to or lower than that of Ru or Mo. AlCu and Al2Cu films at 28nm The lowest resistivity of 9.5 ΩcmCu, lower than Cu.
TSMC leads 1nm R&D
In terms of R&D and commercialization of advanced manufacturing processes, TSMC has always been an industry pioneer, and 1nm is no exception.
As mentioned above, TSMC, Taiwan University of China and MIT jointly developed a contact electrode using semi-metal bismuth as a two-dimensional material, which not only reduces the resistance, but also increases the current, thereby greatly improving energy efficiency. However, the material process is still in the research and development stage and has not been used for mass production. In order to use the semimetal bismuth as the contact electrode of the transistor, it had to use a helium ion beam (HIB) lithography system and devise a “simple deposition process”. This process is only used in R&D production lines, so it is not quite ready for mass production.
At present, TSMC’s 1nm process node is still in the exploratory stage, and the factory is trying various options, and there is no guarantee that the semimetal bismuth will be used in future mass production.
Currently, TSMC’s advanced process lines use tungsten interconnect transistors, while Intel uses cobalt interconnects. Both have their advantages, and both require specific equipment and tools.
Not long ago, it was reported that after TSMC completed the research and development of the 3nm process technology, it turned the team to the future 1.4nm process research and development in June this year.
In addition to TSMC, Samsung and IBM are also developing 1nm process technology.
In today’s integrated circuits, especially processors, transistors are laid flat on a silicon surface, with current flowing from one side to the other. In 2021, IBM and Samsung announced a design method for vertically stacking transistors on a chip, called Vertical Transport Field Effect Transistors (VTFET). Compared to conventional designs, the VTFETs are perpendicular to each other and the current flows vertically. This technology is expected to break through the bottleneck of 1nm process technology.
According to IBM and Samsung, this design has two advantages: first, it can bypass many performance limitations, extending Moore’s Law beyond nanosheet technology, and more importantly, due to higher current, the design reduces energy consumption , estimating that VTFETs will make processors twice as fast or consume 85% less power than chips designed with FinFET transistors.
Intel also stated in 2021 that it plans to cross 1nm by 2024 and complete an Angstrom-level chip design. It is reported that Intel will use its new “Intel 20A” process node and RibbonFET transistors to achieve this goal.
Lithography machine becomes the key
In addition to transistor architecture and material technology, EUV lithography machines are still the key to success in order to achieve mass production of 1nm process chips.
As the only supplier of EUV lithography machines in the world, ASML has always been the focus of TSMC, Samsung and Intel. At present, the advanced EUV lithography machines shipped by ASML are NXE: 3400B, 3400C and 3600D, and the numerical aperture (NA) of these models are all 0.33. Among them, the wafer throughput of 3600D at 30mJ/cm2 reaches 160 wafers, which is 18% higher than that of 3400C. It will become the main equipment of TSMC and Samsung’s 3nm process production lines.
It is reported that the research and development of EUV equipment in cooperation between IMEC and ASML is underway, and Japan’s TEL is also involved. It is expected that the test equipment will be completed in early 2023.
ASML also announced the research and development plan for the next three generations of lithography machines. The models of the three models are NEXT: 5000, EXE: 5000 and EXE: 5200. Starting from EXE:5000, the numerical aperture has been increased to 0.55.
Compared with 0.33NA, 0.55NA equipment has been greatly improved in many aspects, including higher contrast, lower image exposure cost, etc., which is the trend of future development.
Now, the number of lithography machine equipment parts used to produce 5nm/7nm process chips exceeds 100,000, and 40 containers are required for transportation. It is reported that the volume of lithography machines for manufacturing 1nm chips is twice that of 3nm. Since the lithography machine has a lot of parts and requires high-precision assembly, it takes two years for the entire process from delivery to configuration/training of the lithography machine. In this way, the large-scale application of the 0.55NA lithography machine is expected By 2025-2026, it is optimistically estimated that at that time, the industry will start trial production of 1nm process technology.